package CPU.rv64_5stage

import chisel3._
import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage}
import difftest._
import firrtl.options.TargetDirAnnotation

class SimTop extends Module{
  val io = IO(new Bundle{
    val logCtrl   = new LogCtrlIO
    val perfInfo  = new PerfInfoIO
    val uart      = new UARTIO
  })
  val core = Module(new Core)
  val mem  = Module(new Ram2r1w)
  mem.io.imem <> core.io.imem
  mem.io.dmem <> core.io.dmem

  io.uart     := DontCare
  io.perfInfo := DontCare
  io.logCtrl  := DontCare
}

object u_simtop {
  def main(args: Array[String]): Unit = {
    (new ChiselStage).execute(Array("-X", "verilog"), Seq(new ChiselGeneratorAnnotation(() => new SimTop),
      TargetDirAnnotation("build"))
    )
  }
}